Generally, integrated circuit chips include a plurality of devices such as resistors, capacitors, inductors, diodes and transistors wired together into circuits by layers of interconnect structures formed in dielectric layers that are stacked on top of each other.
There are two limiting factors that affect the speed of signal propagation in the interconnect structures, namely, the resistance (R) of the interconnects and the capacitance (C) of the dielectric layer which manifests themselves as an RC delay. Signal delay can be reduced by using low dielectric constant (k) dielectrics, one family of which are called organo-silicate glass (OSG).
However OSG materials are not easily integrated into common integrated circuit fabrication processes. Exposing OSG materials to plasma-based processes can cause image control problems in photoresist layers by release of amines from the OSG material (e.g. photoresist poisoning). Plasma based processing also causes carbon-depletion of the OSG material which leads to increased leakage current flow between unconnected interconnect structures in layers of OSG material as well as interconnect metallurgy/OSG interface adhesion loss.
Therefore there is a need for a method of forming interconnect structures in OSG dielectrics that does not cause photoresist poisoning, is insensitive to OSG carbon-depletion and is less susceptible to interconnect/OSG interface adhesion failure.